Image data compression methods such as a JPEG and MPEG include processing parts suitable for implementation in parallel algorithms. For example, color space conversion processing, DCT (Discrete cosine transform) processing, iDCT (inverse DCT) processing and quantization processing are suitable for implementation in parallel algorithms. JP-2000-69478-A2 and JP-2001-309386-A2 describe using SIMD (Single Instruction Multi Data) instructions and a processor capable of executing the SIMD instruction to process such processing parts suitable for implementation in parallel algorithms.
On the other hand the image data compression methods include processing parts not suitable for implementation in parallel algorithms, also. For example, so called processing VLC (Variable Length Coding) is not suitable for implementation in parallel algorithms. In JP-2000-69478-A2 and JP-2001-309386-A2, the VLC is not processed by software, but instead is processed by a dedicated hardware circuit. A problem associated with such a dedicated hardware circuit is the relatively high cost compared to software implementation.